Priority is claimed to Japanese Patent Application Numbers JP2003-342082, filed on Sep. 30, 2003, and JP2004-251364, filed on Aug. 31, 2004, the disclosures of which are incorporated herein by reference in its entireties.
1. Field of the Invention
The present invention relates to a circuit device and a manufacturing method thereof, more particularly to a circuit device having conductive patterns which are equally spaced apart and a manufacturing method thereof.
2. Description of the Related Art
Conventionally, circuit devices set in electronic equipment have been required to be made smaller, thinner and lighter since the circuit devices are adopted in portable telephones, portable computers and the like.
For example, as the circuit device, a semiconductor device will be described as an example. A wafer-scale CSP having the same size as a chip, which is called a CSP (chip size package), has been recently developed.
FIG. 11 shows a CSP 66 which is slightly larger than chip size. In the CSP 66, a glass epoxy board 65 is adopted as a supporting board. Here, the CSP 66 will be described assuming that a transistor chip T is mounted on the glass epoxy board 65.
On a surface of this glass epoxy board 65, a first electrode 67, a second electrode 68 and a die pad 69 are formed. On a back of the glass epoxy board 65, a first back electrode 70 and a second back electrode 71 are formed. Accordingly, through a through hole TH, the first electrode 67 and the first back electrode 70 are connected to each other. Furthermore, through a through hole TH, the second electrode 68 and the second back electrode 71 are electrically connected to each other. Moreover, the bare transistor chip T is die bonded to the die pad 69 and an emitter electrode of the transistor and the first electrode 67 are connected to each other through a thin metal wire 72. Furthermore, a base electrode of the transistor and the second electrode 68 are connected to each other through a thin metal wire 72. A resin layer 73 is provided on the glass epoxy board 65 so as to cover the transistor chip T.
In the CSP 66, the glass epoxy board 65 is adopted, which leads to an advantage that, unlike the wafer-scale CSP, an extension structure from the chip T to the back electrodes 70 and 71 for external connection can be easily formed and the CSP 66 is manufactured at low cost.
However, in the CSP 66 described above, the glass epoxy board 65 is used as an interposer. Thus, miniaturization and thinning of the CSP 66 had limitations. Consequently, a circuit device 80 requiring no package board, as shown in FIG. 12, was developed (for example, see patent document 1).
With reference to FIG. 12, in the circuit device 80, a circuit element 82 is die bonded to a conductive pattern 81. The circuit element 82 and the conductive pattern 81 are connected to each other through a thin metal wiring 84. A sealing resin 83 covers the circuit element 82, the thin metal wiring 84 and the conductive pattern 81 while exposing a back of the conductive pattern 81. Therefore, the circuit device 80 is configured to require no package board and is formed to be thinner and smaller than the CSP 66.
The conductive pattern 81 in the circuit device 80 is formed by etching a conductive foil. To be more specific, first, a surface of the conductive foil is half etched to form an isolation trench 87. By forming the isolation trench 87, a convex conductive pattern 81 is formed in the surface of the conductive foil. Next, the circuit element 82 is electrically connected to the conductive pattern 81. Thereafter, the sealing resin 83 is formed so as to cover the circuit element and to be filled in the isolation trench 87. Furthermore, the conductive foil is removed from its back until the sealing resin 83 filled in the isolation trench 87 is exposed. Thus, respective conductive patterns 81 are separated. By performing the steps described above, the conductive patterns 81 having a desired shape are formed.
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-076246 (Page 7, FIG. 1)